On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits.

Aswin Sreedhar Alodeep Sanyal Sandip Kundu

Published in: DATE (2008)

Keyphrases

test cases
high speed
delay insensitive
circuit design
low cost
analog vlsi
vlsi circuits
fault diagnosis
built in self test
real time
low voltage
fault model
cmos technology
modeling method
low power
closely related
test set