On test time reduction using pattern overlapping, broadcasting and on-chip decompression.

Martin Chloupek Ondrej Novák Jiri Jenícek

Published in: DDECS (2012)

Keyphrases

pattern matching
low cost
high speed
image processing
image compression
single chip
real time
data mining
compression algorithm
statistical tests
high density
reduction method
vlsi implementation
programmable logic
analog vlsi