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Improvement of gate disturb degradation in SONOS FETs for Vth mismatch compensation in CMOS analog circuits.
Masamichi Suzuki
Atsuhiro Kinoshita
Yuichiro Mitani
Published in:
ICICDT (2013)
Keyphrases
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analog circuits
cmos technology
power dissipation
digital circuits
fault diagnosis
nm technology
power consumption
low cost
neural network
high speed
expert systems
low power
circuit design
significant improvement
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