Steep coverage-ascent directed test generation for shared-memory verification of multicore chips.
Gabriel A. G. AndradeMarleson GrafNícolas PfeiferLuiz C. V. dos SantosPublished in: ICCAD (2018)
Keyphrases
- test generation
- shared memory
- code coverage
- symbolic execution
- test cases
- message passing
- parallel algorithm
- parallel computing
- distributed memory
- multi processor
- test suite
- parallel programming
- static analysis
- high end
- parallel architecture
- software testing
- transactional memory
- quality assurance
- address space
- parallel computation
- parallel machines
- parallel computers
- parallel architectures
- distributed systems
- massively parallel
- test set
- computer systems
- general purpose
- probabilistic model