Test generation using SAT-based bounded model checking for validation of pipelined processors.
Heon-Mo KooPrabhat MishraPublished in: ACM Great Lakes Symposium on VLSI (2006)
Keyphrases
- bounded model checking
- test generation
- model checking
- formal verification
- test cases
- temporal logic
- symbolic execution
- parallel architecture
- linear temporal logic
- design automation
- static analysis
- test sequences
- multi agent systems
- quality assurance
- data flow
- software testing
- shared memory
- search algorithm
- data sets
- integer programming
- decision trees