Login / Signup

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact.

Chan-Yen ChouTuan-Yu HungShin-Yueh YangMing-Chih YewWen-Kun YangKuo-Ning Chiang
Published in: Microelectron. Reliab. (2008)
Keyphrases
  • lower level
  • high speed
  • real time
  • simulation model
  • levels of abstraction
  • massively parallel
  • simulation models
  • failure rate
  • database
  • high impact