Fault secure datapath synthesis using hybrid time and hardware redundancy.
Kaijie WuRamesh KarriPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2004)
Keyphrases
- hardware and software
- low cost
- fault diagnosis
- real time
- fault detection
- computer systems
- multiple faults
- trusted computing
- massively parallel
- neural network
- real time embedded systems
- program synthesis
- computing power
- hardware implementation
- lightweight
- security issues
- computer architecture
- key management
- error detection
- application level
- hardware architecture
- user authentication
- vlsi implementation
- embedded systems
- data acquisition
- protection scheme
- data encryption
- information systems