Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS.
Francisco VeiranoFernando SilveiraLirida A. B. NavinerPublished in: J. Low Power Electron. (2016)
Keyphrases
- low voltage
- random access memory
- charge coupled device
- floating gate
- power supply
- mixed signal
- high speed
- delay insensitive
- focal plane
- random noise
- wide dynamic range
- circuit design
- cmos technology
- noisy data
- modal logic
- noise level
- power consumption
- power management
- missing data
- noise reduction
- design considerations
- multi valued
- photon counting
- cmos image sensor
- power system
- geometric structure
- field effect transistors
- operating point
- chip design
- digital camera
- gaussian noise
- high density
- low cost