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Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing.
Aibin Yan
Zijie Zhai
Lele Wang
Jixiang Zhang
Ningning Cui
Tianming Ni
Xiaoqing Wen
Published in:
ITC-Asia (2021)
Keyphrases
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highly robust
parallel implementation
power consumption
user interface
design process
high density
primal dual
layout design