Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip.
Anshuman ChandraKrishnendu ChakrabartyPublished in: DAC (2001)
Keyphrases
- test data
- low power
- high speed
- low cost
- single chip
- test cases
- mixed signal
- cmos technology
- low power consumption
- power consumption
- test set
- search based testing
- ultra low power
- power dissipation
- training data
- image sensor
- vlsi circuits
- signal processor
- digital signal processing
- nm technology
- testing process
- power reduction
- training set
- image compression
- data sets
- cmos image sensor
- software testing
- embedded systems
- logic circuits
- multi channel
- real time
- test data generation
- decision trees
- training and test data
- focal plane
- data model
- gate array
- compression algorithm