A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.
Hyun-Woo LeeHoon ChoiBeom-Ju ShinKyung-Hoon KimKyung Whan KimJaeil KimKwang Hyun KimJongho JungJae-Hwan KimEun Young ParkJong-Sam KimJong-Hwan KimJin-Hee ChoNam Gyu RyeJun Hyun ChunYunsaing KimChulwoo KimYoung-Jung ChoiByong-Tae ChungPublished in: IEEE J. Solid State Circuits (2012)
Keyphrases
- car racing
- end to end delay
- networked control systems
- control system
- high density
- main memory
- user interface
- real time
- network simulator
- low latency
- network congestion
- control method
- closed loop
- response time
- limit cycle
- ad hoc networks
- controller design
- control algorithm
- packet loss
- quality of service
- neural network
- active queue management
- control law
- fuzzy controller
- control scheme
- prefetching
- control strategy