A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits.

Yuan-Chieh Hsu Sandeep K. Gupta

Published in: IEEE Trans. Computers (1996)

Keyphrases

high speed
test cases
power dissipation
low cost
computationally efficient
fault diagnosis
logic circuits
fault model
asynchronous circuits
partial occlusion
robust estimation