Automatic generation of test sets for SBST of microprocessor IP cores.
Ernesto SánchezMatteo Sonza ReordaGiovanni SquilleroMassimo ViolantePublished in: SBCCI (2005)
Keyphrases
- test set
- training set
- error rate
- processor core
- automatically generate
- design methodology
- special purpose hardware
- training data
- high speed
- embedded dram
- test data
- floating point
- evaluation methodology
- instruction set
- ip networks
- internet protocol
- functional verification
- level parallelism
- data sets
- circuit design
- tcp ip
- database
- ip address
- switched networks
- information extraction
- data mining