Zhichun Zhu

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 12

Top Topics

Top Venues

ACM Trans. Design Autom. Electr. Syst.

Publications

Trung Le, Zhao Zhang, Zhichun Zhu
Polling-Based Memory Interface. ACM Trans. Design Autom. Electr. Syst. 28 (3) (2023)
Peiyun Wu, Trung Le, Zhichun Zhu, Zhao Zhang
Redundant Array of Independent Memory Devices. IEEE Comput. Archit. Lett. 22 (2) (2023)
Muhammad M. Rafique, Zhichun Zhu
Dynamic Page Policy Using Perceptron Learning. MEMSYS (2022)
Trung Le, Zhao Zhang, Zhichun Zhu
POMI: Polling-Based Memory Interface for Hybrid Memory System. ICCD (2021)
Muhammad M. Rafique, Zhichun Zhu
Memory-Side Prefetching Scheme Incorporating Dynamic Page Mode in 3D-Stacked DRAM. IEEE Trans. Parallel Distributed Syst. 32 (11) (2021)
Majed Valad Beigi, Bahareh Pourshirazi, Gokhan Memik, Zhichun Zhu
DeepSwapper: A Deep Learning Based Page Swap Management Scheme for Hybrid Memory Systems. PACT (2020)
Muhammad M. Rafique, Zhichun Zhu
FAPS-3D: feedback-directed adaptive page management scheme for 3D-stacked DRAM. MEMSYS (2019)
Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik
Writeback-Aware LLC Management for PCM-Based Main Memory Systems. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Muhammad M. Rafique, Zhichun Zhu
CAMPS: Conflict-Aware Memory-Side Prefetching Scheme for Hybrid Memory Cube. ICPP (2018)
Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik
WALL: A writeback-aware LLC management for PCM-based main memory systems. DATE (2018)
Bahareh Pourshirazi, Zhichun Zhu
NEMO: an energy-efficient hybrid main memory system for mobile devices. MEMSYS (2017)
Bahareh Pourshirazi, Zhichun Zhu
Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System. IPDPS (2016)
Kun Fang, Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu
Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture. IEEE Trans. Computers 63 (6) (2014)
Suyu Zhang, Zhichun Zhu
Access-Aware Memory Thermal Management. NAS (2014)
Kun Fang, Zhichun Zhu
Conservative row activation to improve memory power efficiency. ICS (2013)
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang
Thermal Modeling and Management of DRAM Systems. IEEE Trans. Computers 62 (10) (2013)
Kun Fang, Long Chen, Zhao Zhang, Zhichun Zhu
Memory Architecture for Integrating Emerging Memory Technologies. PACT (2011)
Hongzhong Zheng, Zhichun Zhu
Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors. IEEE Trans. Computers 59 (8) (2010)
Kun Fang, Hongzhong Zheng, Zhichun Zhu
Heterogeneous Mini-rank: Adaptive, Power-Efficient Memory Architecture. ICPP (2010)
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. ISCA (2009)
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. MICRO (2008)
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David, Zhao Zhang
Software thermal management of dram memory for multicore systems. SIGMETRICS (2008)
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu
Memory Access Scheduling Schemes for Systems with Multi-Core Processors. ICPP (2008)
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang, Howard David
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. ISPASS (2007)
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang
Thermal modeling and management of DRAM memory systems. ISCA (2007)
Zhichun Zhu, Zhao Zhang
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. HPCA (2005)
Zhichun Zhu, Xiaodong Zhang
Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption. IEEE Micro 25 (4) (2005)
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
Design and Optimization of Large Size and Low Overhead Off-Chip Caches. IEEE Trans. Computers 53 (7) (2004)
Zhichun Zhu, Zhao Zhang, Xiaodong Zhang
Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. HPCA (2002)
Zhichun Zhu, Xiaodong Zhang
Access-Mode Predictions for Low-Power Cache Design. IEEE Micro 22 (2) (2002)
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
Cached DRAM for ILP Processor Memory Access Latency Reduction. IEEE Micro 21 (4) (2001)
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
Breaking Address Mapping Symmetry at Multi-levels of Memory Heirarchy to Reduce DRAM Row-buffer Conflicts. J. Instr. Level Parallelism 3 (2001)
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. MICRO (2000)
Xing Du, Xiaodong Zhang, Zhichun Zhu
Memory Hierarchy Considerations for Cost-Effective Cluster Computing. IEEE Trans. Computers 49 (9) (2000)