Zhao Zhang

Publication Activity (10 Years)

Years Active: 1998-2021
Publications (10 Years): 1

Top Topics

Energy Efficient

Top Venues

IEEE Trans. Computers

Concurr. Comput. Pract. Exp.

Publications

Yicheng Wang, Yang Liu, Peiyun Wu, Zhao Zhang
Discreet-PARA: Rowhammer Defense with Low Cost and High Efficiency. ICCD (2021)
Yanan Cao, Long Chen, Zhao Zhang
Memory design for selective error protection. ICCD (2015)
Yanan Cao, Long Chen, Zhao Zhang
Flexible memory: A novel main memory architecture with block-level memory compression. NAS (2015)
Vaibhav Sundriyal, Masha Sosonkina, Zhao Zhang
Automatic runtime frequency-scaling system for energy savings in parallel applications. J. Supercomput. 68 (2) (2014)
Kun Fang, Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu
Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture. IEEE Trans. Computers 63 (6) (2014)
Long Chen, Zhao Zhang
MemGuard: A low cost and energy efficient design to support and enhance memory system reliability. ISCA (2014)
Vaibhav Sundriyal, Masha Sosonkina, Alexander Gaenko, Zhao Zhang
Energy saving strategies for parallel applications with point-to-point communication phases. J. Parallel Distributed Comput. 73 (8) (2013)
Long Chen, Yanan Cao, Zhao Zhang
Free ECC: An efficient error protection for compressed last-level caches. ICCD (2013)
Long Chen, Yanan Cao, Zhao Zhang
CC: A memory error protection scheme with novel address mapping for subranked and low-power memories. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Vaibhav Sundriyal, Masha Sosonkina, Zhao Zhang
Achieving energy efficiency during collective communications. Concurr. Comput. Pract. Exp. 25 (15) (2013)
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang
Thermal Modeling and Management of DRAM Systems. IEEE Trans. Computers 62 (10) (2013)
Kun Fang, Long Chen, Zhao Zhang, Zhichun Zhu
Memory Architecture for Integrating Emerging Memory Technologies. PACT (2011)
Lakshminarasimhan Seshagiri, Meng-Shiou Wu, Masha Sosonkina, Zhao Zhang, Mark S. Gordon, Michael W. Schmidt
Enhancing adaptive middleware for quantum chemistry applications with a database framework. IPDPS Workshops (2010)
Lakshminarasimhan Seshagiri, Masha Sosonkina, Zhao Zhang
Electronic Structure Calculations and Adaptation Scheme in Multi-core Computing Environments. ICCS (1) (2009)
Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, Xiaodong Zhang, P. Sadayappan
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning. PACT (2009)
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, Xiaodong Zhang, P. Sadayappan
Enabling software management for multicore caches with a lightweight hardware support. SC (2009)
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. ISCA (2009)
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. MICRO (2008)
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David, Zhao Zhang
Software thermal management of dram memory for multicore systems. SIGMETRICS (2008)
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, Xiaodong Zhang, P. Sadayappan
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems. HPCA (2008)
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu
Memory Access Scheduling Schemes for Systems with Multi-Core Processors. ICPP (2008)
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang, Howard David
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. ISPASS (2007)
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang
Thermal modeling and management of DRAM memory systems. ISCA (2007)
Tien N. Nguyen, Zhao Zhang
Component-oriented version management for hardware software co-design. CASCON (2006)
Wei Huang, Jiang Lin, Zhao Zhang, J. Morris Chang
Towards Pairing Java Applications on SMT Processors. MASCOTS (2005)
Zhichun Zhu, Zhao Zhang
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. HPCA (2005)
Meng-Shiou Wu, Ricky A. Kendall, Kyle Wright, Zhao Zhang
Performance Modeling and Tuning Strategies of Mixed Mode Collective Communications. SC (2005)
Wei Huang, Jiang Lin, Zhao Zhang, J. Morris Chang
Performance Characterization of Java Applications on SMT Processors. ISPASS (2005)
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
Design and Optimization of Large Size and Low Overhead Off-Chip Caches. IEEE Trans. Computers 53 (7) (2004)
Zhichun Zhu, Zhao Zhang, Xiaodong Zhang
Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. HPCA (2002)
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
Cached DRAM for ILP Processor Memory Access Latency Reduction. IEEE Micro 21 (4) (2001)
Zhao Zhang, Xiaodong Zhang
Fast Bit-Reversals on Uniprocessors and Shared-Memory Multiprocessors. SIAM J. Sci. Comput. 22 (6) (2001)
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
Breaking Address Mapping Symmetry at Multi-levels of Memory Heirarchy to Reduce DRAM Row-buffer Conflicts. J. Instr. Level Parallelism 3 (2001)
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. MICRO (2000)
Yong Yan, Xiaodong Zhang, Zhao Zhang
Cacheminer: A Runtime Approach to Exploit Cache Locality on SMP. IEEE Trans. Parallel Distributed Syst. 11 (4) (2000)
Zhao Zhang, Xiaodong Zhang
Cache-Optimal Methods for Bit-Reversals. SC (1999)
Yong Yan, Xiaodong Zhang, Zhao Zhang
A memory-layout oriented run-time technique for locality optimization. ICPP (1998)