Cached DRAM for ILP Processor Memory Access Latency Reduction.
Zhao ZhangZhichun ZhuXiaodong ZhangPublished in: IEEE Micro (2001)
Keyphrases
- access latency
- memory access
- main memory
- memory subsystem
- instruction set
- external memory
- prefetching
- memory management
- database management systems
- data structure
- response time
- dynamic random access memory
- data access
- random access memory
- cache hit ratio
- index structure
- access patterns
- operating system
- embedded dram
- database systems
- database
- shared memory
- scheduling algorithm
- high volume
- flash memory
- memory space
- data storage
- message passing
- ibm zenterprise
- high speed