Yuan Zhou

Publication Activity (10 Years)

Years Active: 2013-2019
Publications (10 Years): 8

Top Topics

Analog To Digital Converter

Power Consumption

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yuan Zhou, Benwei Xu, Yun Chiu
A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC. IEEE J. Solid State Circuits 54 (8) (2019)
Hongda Xu, Hai Huang, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu
A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS. IEEE J. Solid State Circuits 54 (2) (2019)
Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu
A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS. IEEE J. Solid State Circuits 53 (3) (2018)
Hongda Xu, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu
28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS. ISSCC (2017)
Benwei Xu, Yuan Zhou, Yun Chiu
A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS. IEEE J. Solid State Circuits 52 (4) (2017)
Benwei Xu, Yuan Zhou, Yun Chiu
A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS. VLSI Circuits (2016)
Sudipta Sarkar, Yuan Zhou, Brian Elies, Yun Chiu
PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Yuan Zhou, Benwei Xu, Yun Chiu
A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector. IEEE J. Solid State Circuits 50 (4) (2015)
Sudipta Sarkar, Yuan Zhou, Yun Chiu
PN-assisted deterministic digital calibration of split two-step ADC to over 14-bit accuracy. MWSCAS (2014)
Yuan Zhou, Benwei Xu, Yun Chiu
A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration. VLSIC (2014)
Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu
A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system. CICC (2014)
Yuan Zhou, Yun Chiu
Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC. MWSCAS (2013)