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28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS.
Hongda Xu
Yongda Cai
Ling Du
Yuan Zhou
Benwei Xu
Datao Gong
Jingbo Ye
Yun Chiu
Published in:
ISSCC (2017)
Keyphrases
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power consumption
clock gating
nm technology
low power
cmos technology
energy efficiency
power management
power saving
power reduction
battery life
infrared
power dissipation
energy saving
single chip
data center
x ray
battery powered
high speed
low power consumption
sar images