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Benwei Xu
ORCID
Publication Activity (10 Years)
Years Active: 2013-2019
Publications (10 Years): 9
Top Topics
Nm Technology
Hd Video
Clock Gating
Power Consumption
Top Venues
IEEE J. Solid State Circuits
ISSCC
IEEE Trans. Circuits Syst. I Regul. Pap.
VLSIC
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Publications
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Yuan Zhou
,
Benwei Xu
,
Yun Chiu
A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC.
IEEE J. Solid State Circuits
54 (8) (2019)
Hongda Xu
,
Hai Huang
,
Yongda Cai
,
Ling Du
,
Yuan Zhou
,
Benwei Xu
,
Datao Gong
,
Jingbo Ye
,
Yun Chiu
A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS.
IEEE J. Solid State Circuits
54 (2) (2019)
Hongda Xu
,
Yongda Cai
,
Ling Du
,
Yuan Zhou
,
Benwei Xu
,
Datao Gong
,
Jingbo Ye
,
Yun Chiu
28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS.
ISSCC
(2017)
Sudipta Sarkar
,
Benwei Xu
,
Brian Elies
,
Yun Chiu
An 8b 1.39GS/S 0.85V two-step ADC with background comparator offset calibration.
MWSCAS
(2017)
Benwei Xu
,
Yuan Zhou
,
Yun Chiu
A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS.
IEEE J. Solid State Circuits
52 (4) (2017)
Shuang Zhu
,
Benwei Xu
,
Bo Wu
,
Kiran Soppimath
,
Yun Chiu
A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM.
IEEE J. Solid State Circuits
51 (8) (2016)
Bo Wu
,
Shuang Zhu
,
Benwei Xu
,
Yun Chiu
A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR.
IEEE J. Solid State Circuits
51 (12) (2016)
Bo Wu
,
Shuang Zhu
,
Benwei Xu
,
Yun Chiu
15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS.
ISSCC
(2016)
Benwei Xu
,
Yuan Zhou
,
Yun Chiu
A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS.
VLSI Circuits
(2016)
Benwei Xu
,
Yun Chiu
Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
(5) (2015)
Yuan Zhou
,
Benwei Xu
,
Yun Chiu
A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector.
IEEE J. Solid State Circuits
50 (4) (2015)
Shuang Zhu
,
Benwei Xu
,
Bo Wu
,
Kiran Soppimath
,
Yun Chiu
10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM.
CICC
(2015)
Yuan Zhou
,
Benwei Xu
,
Yun Chiu
A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration.
VLSIC
(2014)
Benwei Xu
,
Yun Chiu
Background calibration of time-interleaved ADC using direct derivative information.
ISCAS
(2013)