Yiqiang Ding

Publication Activity (10 Years)

Years Active: 1999-2015
Publications (10 Years): 1

Top Topics

Multicore Processors

Memory Hierarchy

Parallel Algorithm

Top Venues

J. Comput. Sci. Eng.

Publications

Yiqiang Ding, Wei Zhang
Exploiting Static Non-Uniform Cache Architectures for Hard Real-Time Computing. J. Comput. Sci. Eng. 9 (4) (2015)
Lan Wu, Yiqiang Ding, Wei Zhang
Comparing Separate and Statically-Partitioned Caches for Time-Predictable Multicore Processors. J. Comput. Sci. Eng. 8 (1) (2014)
Yiqiang Ding, Wei Zhang
WCET analysis of static NUCA caches. IPCCC (2014)
Lan Wu, Yiqiang Ding, Wei Zhang
Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-Caches. HPCC/CSS/ICESS (2014)
Wei Zhang, Yiqiang Ding
Exploiting Standard Deviation of CPI to Evaluate Architectural Time-Predictability. J. Comput. Sci. Eng. 8 (1) (2014)
Yiqiang Ding, Wei Zhang
Bounding the Worst-Case Execution Time of Static NUCA Caches. HPCC/CSS/ICESS (2014)
Yiqiang Ding, Wei Zhang
Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency. EUC (2014)
Yiqiang Ding, Wei Zhang
Multicore Real-Time Scheduling to Reduce Inter-Thread Cache Interferences. J. Comput. Sci. Eng. 7 (1) (2013)
Yiqiang Ding, Wei Zhang
On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors. ISQED (2013)
Wei Zhang, Yiqiang Ding
Standard deviation of CPI: A new metric to evaluate architectural time predictability. ASAP (2013)
Yiqiang Ding, Lan Wu, Wei Zhang
Bounding Worst-Case DRAM Performance on Multicore Processors. J. Comput. Sci. Eng. 7 (1) (2013)
Yiqiang Ding, Wei Zhang
Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches. J. Comput. Sci. Eng. 7 (4) (2013)
Wei Zhang, Yiqiang Ding
Hybrid SPM-cache architectures to achieve high time predictability and performance. ASAP (2013)
Yiqiang Ding, Wei Zhang
Architectural time-predictability factor (ATF): a metric to evaluate time predictability of processors. SIGBED Rev. 9 (4) (2012)
Yiqiang Ding, Wei Zhang
Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches. J. Comput. Sci. Eng. 6 (1) (2012)
Yiqiang Ding, Wei Zhang
Multicore-Aware Code Positioning to Improve Worst-Case Performance. ISORC (2011)
Yiqiang Ding, Wei Zhang
Improving the static real-time scheduling on multicore processors by reducing worst-case inter-thread cache interferences. ACM Southeast Regional Conference (2010)
Yiqiang Ding, Wei Zhang
Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time. IEEE Trans. Computers 59 (6) (2010)
Yiqiang Ding, Jun Yan, Wei Zhang
Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. J. Comput. Sci. Eng. 3 (1) (2009)
Yiqiang Ding
An improvement of GNY logic for the reflection attacks. J. Comput. Sci. Technol. 14 (6) (1999)