Jun Yan

Publication Activity (10 Years)

Years Active: 2005-2016
Publications (10 Years): 1

Top Topics

Parallel Architectures

Computing Power

Multicore Processors

Top Venues

Int. J. Embed. Syst.

J. Comput. Sci. Eng.

Publications

Jun Yan, Wei Zhang
Priority L2 cache design for time predictability. Int. J. Embed. Syst. 8 (5/6) (2016)
Wei Zhang, Jun Yan
Static Timing Analysis of Shared Caches for Multicore Processors. J. Comput. Sci. Eng. 6 (4) (2012)
Jun Yan, Wei Zhang
Computing and Reducing Transient Error Propagation in Registers. J. Comput. Sci. Eng. 5 (2) (2011)
Jun Yan, Wei Zhang
An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors. J. Comput. Sci. Eng. 5 (2) (2011)
Jun Yan, Wei Zhang
Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches. J. Comput. Sci. Eng. 5 (1) (2011)
Jun Yan, Wei Zhang
Time-Predictable L2 Cache Design for High-Performance Real-Time Systems. RTCSA (2010)
Jun Yan, Wei Zhang
Design and implementation of hybrid multicore simulators. Int. J. Embed. Syst. 4 (3/4) (2010)
Yiqiang Ding, Jun Yan, Wei Zhang
Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. J. Comput. Sci. Eng. 3 (1) (2009)
Wei Zhang, Jun Yan
Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches. RTCSA (2009)
Jun Yan, Wei Zhang
Exploiting virtual registers to reduce pressure on real registers. ACM Trans. Archit. Code Optim. 4 (4) (2008)
Jun Yan, Wei Zhang
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches. IEEE Real-Time and Embedded Technology and Applications Symposium (2008)
Jun Yan, Wei Zhang
A time-predictable VLIW processor and its compiler support. Real Time Syst. 38 (1) (2008)
Jun Yan, Wei Zhang
Analyzing the worst-case execution time for instruction caches with prefetching. ACM Trans. Embed. Comput. Syst. 8 (1) (2008)
Jun Yan, Wei Zhang
Virtual Registers: Reducing Register Pressure Without Enlarging the Register File. HiPEAC (2007)
Jun Yan, Wei Zhang
WCET analysis of instruction caches with prefetching. LCTES (2007)
Jun Yan, Wei Zhang
Evaluating instruction cache vulnerability to transient errors. SIGARCH Comput. Archit. News 35 (4) (2007)
Jun Yan, Wei Zhang
Hybrid multi-core architecture for boosting single-threaded performance. SIGARCH Comput. Archit. News 35 (1) (2007)
Jun Yan, Wei Zhang
Compiler-guided register reliability improvement against soft errors. EMSOFT (2005)