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Yeonbok Lee
Publication Activity (10 Years)
Years Active: 2009-2019
Publications (10 Years): 3
Top Topics
Correlation Matrix
Efficient Inference
Wearable Devices
Speech Enhancement
Top Venues
FPT
IWAENC
CGO
DATE
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Publications
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Minwook Ahn
,
Seok Joong Hwang
,
Wonsub Kim
,
Seungrok Jung
,
Yeonbok Lee
,
Mookyoung Chung
,
Woohyung Lim
,
Young Joon Kim
AIX: A high performance and energy efficient inference accelerator on FPGA for a DNN-based commercial speech recognition.
DATE
(2019)
Jun Hyung Kim
,
Jazzson Park
,
Minwook Ahn
,
Yeonbok Lee
,
Wonsub Kim
,
Hyung-Min Park
Online Speech Dereverberation Using RLS-WPE Based on a Full Spatial Correlation Matrix Integrated in a Speech Enhancement System.
IWAENC
(2018)
Bernhard Egger
,
Hochan Lee
,
Duseok Kang
,
Mansureh S. Moghaddam
,
Youngchul Cho
,
Yeonbok Lee
,
Sukjin Kim
,
Soonhoi Ha
,
Kiyoung Choi
A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures.
CGO
(2017)
Do-Hyung Kim
,
Seokhwan Jo
,
Kiseok Kwon
,
Yeonbok Lee
,
Seungwon Lee
,
Young-Hwan Park
,
Sukjin Kim
,
Jaehyun Kim
,
Shihwa Lee
Ultra-low-power voice trigger for wearable devices.
ICCE-TW
(2015)
Ho Yang
,
Jaewook Shim
,
Jihoon Bang
,
Yeonbok Lee
Software-based giga-bit WLAN platform.
ICCE
(2014)
Young-Hwan Park
,
Keshava Prasad
,
Yeonbok Lee
,
Kitaek Bae
,
Ho Yang
Scalable radio processor architecture for modern wireless communications.
FPT
(2014)
Yeonbok Lee
,
Takeshi Matsumoto
,
Masahiro Fujita
On-chip dynamic signal sequence slicing for efficient post-silicon debugging.
ASP-DAC
(2011)
Yeonbok Lee
,
Takeshi Matsumoto
,
Masahiro Fujita
An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(7) (2011)
Yeonbok Lee
,
Takeshi Matsumoto
,
Masahiro Fujita
Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging.
ICCD
(2010)
Yeonbok Lee
,
Tasuku Nishihara
,
Takeshi Matsumoto
,
Masahiro Fujita
A Post-Silicon Debug Support Using High-Level Design Description.
Asian Test Symposium
(2009)