Xiaoheng Chen

Publication Activity (10 Years)

Years Active: 2009-2013
Publications (10 Years): 0

Top Topics

Decoding Algorithm

Low Density Parity Check

Constraint Satisfaction Problems

Top Venues

IEEE Trans. Commun.

Publications

Chung-Li Wang, Xiaoheng Chen, Zongwang Li, Shaohua Yang
A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes. IEEE Trans. Commun. 61 (1) (2013)
Xiaoheng Chen, Shu Lin, Venkatesh Akella
Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2012)
Chung-Li Wang, Xiaoheng Chen, Zongwang Li, Shaohua Yang
A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes CoRR (2012)
Xiaoheng Chen, Chung-Li Wang
Exploiting the shift property of structured LDPC codes for reduced-complexity sliced message passing based decoder design. ICNC (2012)
Xiaoheng Chen, Chung-Li Wang
High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2012)
Xiaoheng Chen, Venkatesh Akella
Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA. ACM Trans. Reconfigurable Technol. Syst. 4 (4) (2011)
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2011)
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2011)
Xiaoheng Chen, Shu Lin, Venkatesh Akella
QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs (10) (2010)
Xiaoheng Chen, Qin Huang, Shu Lin, Venkatesh Akella
FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes. Allerton (2009)
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing. DATE (2009)