Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes.
Xiaoheng ChenJingyu KangShu LinVenkatesh AkellaPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2011)
Keyphrases
- hardware implementation
- ldpc codes
- decoding algorithm
- error correction
- message passing
- low density parity check
- fpga implementation
- error detection
- signal processing
- efficient implementation
- field programmable gate array
- rate allocation
- image transmission
- channel coding
- image processing algorithms
- end to end
- constraint satisfaction
- image processing
- source coding
- noise model
- error propagation
- distributed systems
- markov random field