Wei Cao

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 18

Top Topics

Matrix Multiplication

Reconfigurable Architecture

Stream Processing

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEICE Trans. Inf. Syst.

Publications

Jialin Chen, Zhiqiang Cai, Ke Xu, Di Wu, Wei Cao
Qubit-Wise Architecture Search Method for Variational Quantum Circuits. CoRR (2024)
Xitian Fan, Guangwei Xie, Zhongcheng Huang, Wei Cao, Lingli Wang
Acceleration of Rotated Object Detection on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Siyu Xiong, Guoqing Wu, Xitian Fan, Xuan Feng, Zhongcheng Huang, Wei Cao, Xuegong Zhou, Shijin Ding, Jinhua Yu, Lingli Wang, Zhifeng Shi
MRI-based brain tumor segmentation using FPGA-accelerated neural network. BMC Bioinform. 22 (1) (2021)
Jingbo Gao, Yu Qian, Yihan Hu, Xitian Fan, Wai-Shing Luk, Wei Cao, Lingli Wang
LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA. FPT (2021)
Di Wu, Xitian Fan, Wei Cao, Lingli Wang
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 29 (5) (2021)
Yue Li, Wei Cao, Xuegong Zhou, Lingli Wang
A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN Applications. FPT (2020)
Mingjun Jiao, Yue Li, Pengbo Dang, Wei Cao, Lingli Wang
A High Performance FPGA-Based Accelerator Design for End-to-End Speaker Recognition System. FPT (2019)
Cheng Luo, Wei Cao, Lingli Wang, Philip H. W. Leong
RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks. IEICE Trans. Inf. Syst. (5) (2019)
Di Wu, Wei Cao, Lingli Wang
SpWMM: A High-Performance Sparse-Winograd Matrix-Matrix Multiplication Accelerator for CNNs. FPT (2019)
Cheng Luo, Yuhua Wang, Wei Cao, Philip H. W. Leong, Lingli Wang
RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks. FPL (2018)
Liang Xie, Xitian Fan, Wei Cao, Lingli Wang
High Throughput CNN Accelerator Design Based on FPGA. FPT (2018)
Di Wu, Jin Chen, Wei Cao, Lingli Wang
A Novel Low-Communication Energy-Efficient Reconfigurable CNN Acceleration Architecture. FPL (2018)
Xitian Fan, Di Wu, Wei Cao, Wayne Luk, Lingli Wang
Stream Processing Dual-Track CGRA for Object Inference. IEEE Trans. Very Large Scale Integr. Syst. 26 (6) (2018)
Li Jiao, Cheng Luo, Wei Cao, Xuegong Zhou, Lingli Wang
Accelerating low bit-width convolutional neural networks with embedded FPGA. FPL (2017)
Qi Zhan, Min Gao, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang
High performance Deformable Part Model accelerator based on FPGA. FPT (2016)
Xitian Fan, Huimin Li, Wei Cao, Lingli Wang
DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications. FPL (2016)
Huimin Li, Xitian Fan, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang
A high performance FPGA-based accelerator for large-scale convolutional neural networks. FPL (2016)
Yangjie Zhang, Wei Cao, Lingli Wang
Implementation of high performance hardware architecture of face recognition algorithm based on local binary pattern on FPGA. ASICON (2015)
Chen Liang, Chenlu Wu, Xuegong Zhou, Wei Cao, Shengye Wang, Lingli Wang
An FPGA-cluster-accelerated match engine for content-based image retrieval. FPT (2013)
Shengye Wang, Wei Cao, Lingli Wang, Na Wang, Ping Tao
A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly. ASICON (2013)
Shengye Wang, Chen Liang, Xuegong Zhou, Wei Cao, Chenlu Wu, Xitian Fan, Lingli Wang
A hardware implementation of Bag of Words and Simhash for image recognition. FPT (2013)
Xitian Fan, Chenlu Wu, Wei Cao, Xuegong Zhou, Shengye Wang, Lingli Wang
Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA. FPT (2013)
Chenlu Wu, Wei Cao, Xuegong Zhou, Lingli Wang, Fang Wang, Baodi Yuan
A reconfigurable floating-point FFT architecture. ASICON (2013)
Shuai Chen, Jialin Chen, Kanwen Wang, Wei Cao, Lingli Wang
A permutation network for configurable and scalable FFT processors. ASICON (2011)
Kanwen Wang, Jialin Chen, Wei Cao, Ying Wang, Lingli Wang, Jiarong Tong
A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design. IEEE Trans. Circuits Syst. II Express Briefs (7) (2011)
Kanwen Wang, Shuai Chen, Wei Cao, Lingli Wang, Jiarong Tong
A coarse-grained reconfigurable computing unit. ASICON (2011)
Wei Cao, Hui Hou, Jiarong Tong, Jinmei Lai, Hao Min
A high-performance reconfigurable VLSI architecture for vbsme in H.264. IEEE Trans. Consumer Electron. 54 (3) (2008)
Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min
A high-performance reconfigurable 2-D transform architecture for H.264. ICECS (2008)
Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min
A novel dynamic reconfigurable VLSI architecture for H.264 transforms. APCCAS (2008)
Hui Hou, Wei Cao, Fan-jiong Zhang, Jinmei Lai, Jiarong Tong
High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform. ICECS (2008)