V. K. Agrawal

Publication Activity (10 Years)

Years Active: 1985-2017
Publications (10 Years): 2

Top Topics

Evaluation Campaigns

Hardware Implementation

Reconfigurable Architecture

Top Venues

Publications

Santosh Kumar, J. Manikandan, V. K. Agrawal
Hardware implementation of support vector machine classifier using reconfigurable architecture. ICACCI (2017)
Senthilkumar E., J. Manikandan, V. K. Agrawal
Design and evaluation of FPGA based frequency demodulators. ICACCI (2015)
Senthilkumar E., J. Manikandan, V. K. Agrawal
FPGA implementation of dynamically tunable filters. ICACCI (2014)
A. Divya Rao, Piyush Kumar, Neha Nain, V. K. Agrawal
MATLAB-Based GUI Development for Stochastic Noise Analysis of Tri-Axial Gyroscopes. ISED (2014)
J. Manikandan, V. K. Agrawal, B. Venkataramani
Design of a Biometric Security System Using Support Vector Machine Classifier. ICACNI (2013)
Kunal Yogeshkumar Parikh, J. Manikandan, V. K. Agrawal
Design and Evaluation of N-Module Reconfigurable Systems. ICACNI (2013)
Santanu Sarma, V. K. Agrawal, Subramanya Udupa
Software-Based Resolver-to-Digital Conversion Using a DSP. IEEE Trans. Ind. Electron. 55 (1) (2008)
B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal
A New ATPG Technique (ExpoTan) for Testing Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (1) (2007)
P. Balasubramanian, P. M. Aravindakshan, K. Parameswaran, V. K. Agrawal
A simple scheme for PSK demodulation. Microprocess. Microsystems 28 (7) (2004)
B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal
A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (2) (2004)
B. K. S. V. L. Varaprasad, L. M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal
An Efficient Test Pattern Generation Scheme for an On Chip BIST. VLSI Design 2001 (4) (2001)
J. K. Kishore, Lalit M. Patnaik, V. Mani, V. K. Agrawal
Genetic programming based pattern classification with feature space partitioning. Inf. Sci. 131 (1-4) (2001)
J. K. Kishore, Lalit M. Patnaik, V. Mani, V. K. Agrawal
Application of genetic programming for multicategory pattern classification. IEEE Trans. Evol. Comput. 4 (3) (2000)
F. Thomas, M. M. Nayak, Subramanya Udupa, J. K. Kishore, V. K. Agrawal
A hardware/software codesign for improved data acquisition in a processor based embedded system. Microprocess. Microsystems 24 (3) (2000)
F. Thomas, J. K. Kishore, K. M. Bharadwaj, M. M. Nayak, V. K. Agrawal
Design and implementation of a wheel speed measurement circuit using field programmable gate arrays in a spacecraft. Microprocess. Microsystems 22 (9) (1999)
J. K. Kishore, R. S. Manjunatha, V. K. Agrawal, N. K. Malik, Prem Shankar Goel
A Real Time Fault Tolerant Microprocessor Based On-Board Computer System for INSAT-2 Spacecraft. FTRTFT (1994)
Sajal K. Das, Dilip Sarkar, V. K. Agrawal, Lalit M. Patnaik
Extended colored Petri net: An efficient tool for analyzing concurrent systems. Inf. Sci. 54 (3) (1991)
Sajal K. Das, V. K. Agrawal, Dilip Sarkar, Lalit M. Patnaik, Prem Shankar Goel
Reflexive Incidence Matrix (RIM) Representation of Petri Nets. IEEE Trans. Software Eng. 13 (6) (1987)
V. K. Agrawal, Lalit M. Patnaik, Prem Shankar Goel
Towards formal specification of a distributed computing system. Int. J. Parallel Program. 14 (5) (1985)