An Efficient Test Pattern Generation Scheme for an On Chip BIST.

B. K. S. V. L. Varaprasad L. M. Patnaik Hirisave S. Jamadagni V. K. Agrawal

Published in: VLSI Design (2001)

Keyphrases

vlsi implementation
built in self test
high speed
learning scheme
real time
multiresolution
low cost
classification scheme
computationally efficient
video coding
highly efficient
bi directional
vlsi design