Toru Iwata

Publication Activity (10 Years)

Years Active: 1996-2018
Publications (10 Years): 1

Top Topics

Probability Distribution

Top Venues

IEICE Electron. Express

Publications

Tsuyoshi Ebuchi, Taku Toshikawa, Seiji Watanabe, Yutaka Terada, Toru Iwata
An ultra-wide range (0.01-240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generator. IEICE Electron. Express 15 (3) (2018)
Tsuyoshi Ebuchi, Taku Toshikawa, Seiji Watanabe, Tomohiro Tsuchiya, Yutaka Terada, Tomoko Chiba, Keijiro Umehara, Toru Iwata, Takefumi Yoshikawa
A jitter suppression technique against data pattern dependency on high-speed interfaces for highly integrated SoCs. IEICE Electron. Express 11 (22) (2014)
Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa
An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration. IEEE J. Solid State Circuits 46 (4) (2011)
Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi
An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics. IEEE Trans. Very Large Scale Integr. Syst. 16 (9) (2008)
Takefumi Yoshikawa, Tsuyoshi Ebuchi, Yukio Arima, Toru Iwata
A Spread Spectrum Clock Generator Using Digital Tracking Scheme. IEICE Trans. Electron. (6) (2005)
Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. IEEE Trans. Very Large Scale Integr. Syst. 5 (4) (1997)
Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. ISLPED (1996)