Taras Iakymchuk

Publication Activity (10 Years)

Years Active: 2011-2019
Publications (10 Years): 9

Top Topics

Network Architecture

Detection Algorithm

Top Venues

IEEE Trans. Biomed. Circuits Syst.

Publications

Leandro D. Medus, Taras Iakymchuk, José Vicente Francés-Víllora, Manuel Bataller-Mompeán, Alfredo Rosado Muñoz
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks. IEEE Access 7 (2019)
Juan Barrios-Aviles, Taras Iakymchuk, Jorge Samaniego, Alfredo Rosado Muñoz
An Event-based Fast Movement Detection Algorithm for a Positioning Robot Using POWERLINK Communication. CoRR (2017)
Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. IEEE Trans. Biomed. Circuits Syst. 11 (5) (2017)
Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems. ISCAS (2017)
Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Stephen B. Furber, Bernabé Linares-Barranco
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems. ISCAS (2017)
Silvia Casans Berga, Alfredo Rosado Muñoz, Taras Iakymchuk
Novel Resistance Measurement Method: Analysis of Accuracy and Thermal Dependence with Applications in Fiber Materials. Sensors 16 (12) (2016)
Juan Barrios-Aviles, Taras Iakymchuk, Alfredo Rosado Muñoz, José V. Francés-Víllora, Manuel Bataller-Mompeán, Juan Guerrero-Martínez
Event-based encoding from digital magnetic compass and ultrasonic distance sensor for navigation in mobile systems. INDIN (2016)
Taras Iakymchuk, Alfredo Rosado Muñoz, Manuel Bataller-Mompeán, José Vicente Francés-Víllora, Emmanuel Ovie Osimiry
Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices. IEEE Trans. Computers 65 (11) (2016)
Taras Iakymchuk, Alfredo Rosado Muñoz, Juan Guerrero-Martínez, Manuel Bataller-Mompeán, José V. Francés-Víllora
Simplified spiking neural network architecture and STDP learning algorithm applied to image classification. EURASIP J. Image Video Process. 2015 (2015)
Taras Iakymchuk, Alfredo Rosado, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno
An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links. ISCAS (2014)
Taras Iakymchuk, Alfredo Rosado, Emilio Soria-Olivas, Manuel Bataller
Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noise. ICECS (2012)
Taras Iakymchuk, Alfredo Rosado, José V. Francés, Manuel Bataller
Fast spiking neural network architecture for low-cost FPGA devices. ReCoSoC (2012)
Alfredo Rosado, Taras Iakymchuk, Manuel Bataller, Marek Wegrzyn
Hardware-efficient matrix inversion algorithm for complex adaptive systems. ICECS (2012)
Taras Iakymchuk, Maciej Nikodem, Krzysztof Kepa
Temperature-based covert channel in FPGA systems. ReCoSoC (2011)