José Vicente Francés-Víllora

Publication Activity (10 Years)

Years Active: 2015-2019
Publications (10 Years): 5

Top Topics

Hardware Design

Multi Layer Perceptron

Top Venues

Comput. Electr. Eng.

IEEE Trans. Ind. Informatics

IEEE Trans. Computers

Publications

Leandro D. Medus, Taras Iakymchuk, José Vicente Francés-Víllora, Manuel Bataller-Mompeán, Alfredo Rosado Muñoz
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks. IEEE Access 7 (2019)
Manuel Bataller-Mompeán, José Miguel Martínez-Villena, Alfredo Rosado Muñoz, José Vicente Francés-Víllora, Juan Guerrero-Martínez, Marek Wegrzyn, Marian Adamski
Support Tool for the Combined Software/Hardware Design of On-Chip ELM Training for SLFF Neural Networks. IEEE Trans. Ind. Informatics 12 (3) (2016)
Taras Iakymchuk, Alfredo Rosado Muñoz, Manuel Bataller-Mompeán, José Vicente Francés-Víllora, Emmanuel Ovie Osimiry
Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices. IEEE Trans. Computers 65 (11) (2016)
José Vicente Francés-Víllora, Alfredo Rosado Muñoz, José M. Martínez-Villena, Manuel Bataller-Mompeán, Juan-Francisco Guerrero-Martínez, Marek Wegrzyn
Hardware implementation of real-time Extreme Learning Machine in FPGA: Analysis of precision, resource occupation and performance. Comput. Electr. Eng. 51 (2016)
José Miguel Martínez-Villena, José Vicente Francés-Víllora, Alfredo Rosado Muñoz, Manuel Bataller-Mompeán, Juan-Francisco Guerrero-Martínez, Marek Wegrzyn, Marian Adamski
Design environment for hardware generation of SLFF neural network topologies with ELM training capability. INDIN (2015)