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Tameesh Suri
Publication Activity (10 Years)
Years Active: 2007-2017
Publications (10 Years): 1
Top Topics
Solid State
Real World
Databases
Disk Drives
Top Venues
ARCS
IEEE Trans. Computers
SIGMETRICS
ICPE
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Publications
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Tameesh Suri
,
Aneesh Aggarwal
Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUs.
ARCS
(2017)
Qiumin Xu
,
Huzefa Siyamwala
,
Mrinmoy Ghosh
,
Manu Awasthi
,
Tameesh Suri
,
Zvika Guz
,
Anahita Shayesteh
,
Vijay Balakrishnan
Performance Characterization of Hyperscale Applicationson on NVMe SSDs.
SIGMETRICS
(2015)
Manu Awasthi
,
Tameesh Suri
,
Zvika Guz
,
Anahita Shayesteh
,
Mrinmoy Ghosh
,
Vijay Balakrishnan
System-Level Characterization of Datacenter Applications.
ICPE
(2015)
Qiumin Xu
,
Huzefa Siyamwala
,
Mrinmoy Ghosh
,
Tameesh Suri
,
Manu Awasthi
,
Zvika Guz
,
Anahita Shayesteh
,
Vijay Balakrishnan
Performance analysis of NVMe SSDs and their implication on real world databases.
SYSTOR
(2015)
Meltem Ozsoy
,
Dmitry Ponomarev
,
Nael B. Abu-Ghazaleh
,
Tameesh Suri
SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors.
IEEE Trans. Computers
63 (2) (2014)
Meltem Ozsoy
,
Dmitry Ponomarev
,
Nael B. Abu-Ghazaleh
,
Tameesh Suri
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors.
Conf. Computing Frontiers
(2011)
Tameesh Suri
,
Aneesh Aggarwal
Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration.
Int. J. Parallel Program.
38 (3-4) (2010)
Tameesh Suri
,
Aneesh Aggarwal
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration.
VLSI Design
(2009)
Tameesh Suri
,
Aneesh Aggarwal
Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration.
Conf. Computing Frontiers
(2009)
Tameesh Suri
,
Aneesh Aggarwal
Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware.
HiPC
(2008)
Tameesh Suri
Improving instruction level parallelism through reconfigurable units in superscalar processors.
SIGARCH Comput. Archit. News
35 (3) (2007)