Surin Kittitornkun

Publication Activity (10 Years)

Years Active: 2000-2021
Publications (10 Years): 4

Top Topics

Malware Detection

Correlation Analysis

Reverse Engineering

Sorting Algorithms

Top Venues

J. Mobile Multimedia

IEICE Trans. Commun.

Int. J. Inf. Sec.

J. Supercomput.

Publications

Apisit Rattanatranurak, Surin Kittitornkun
Optimizing MultiStack Parallel (MSP) Sorting Algorithm. J. Mobile Multimedia 17 (4) (2021)
Apisit Rattanatranurak, Surin Kittitornkun
A MultiStack Parallel (MSP) Partition Algorithm Applied to Sorting. J. Mobile Multimedia 16 (3) (2020)
Khamphao Sisaat, Surin Kittitornkun, Hiroaki Kikuchi, Chaxiong Yukonhiatou, Masato Terada, Hiroshi Ishii
A Spatio-Temporal malware and country clustering algorithm: 2012 IIJ MITF case study. Int. J. Inf. Sec. 16 (5) (2017)
Ratthaslip Ranokphanuwat, Surin Kittitornkun
Parallel Partition and Merge QuickSort (PPMQSort) on Multicore CPUs. J. Supercomput. 72 (3) (2016)
Khamphao Sisaat, Hiroaki Kikuchi, Shunji Matsuo, Masato Terada, Masashi Fujiwara, Surin Kittitornkun
Time Zone Correlation Analysis of Malware/Bot Downloads. IEICE Trans. Commun. (7) (2013)
N. Hiroguchi, Hiroaki Kikuchi, Khamphao Sisaat, Surin Kittitornkun
Geographical Visualization of Malware Download for Anomaly Detection. AsiaJCIS (2012)
Thinh Ngoc Tran, Surin Kittitornkun
Massively Parallel Cuckoo Pattern Matching Applied for NIDS/NIPS. DELTA (2010)
Thinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama
PAMELA: Pattern Matching Engine with Limited-Time Update for NIDS/NIPS. IEICE Trans. Inf. Syst. (5) (2009)
Tran Ngoc Thinh, Surin Kittitornkun, Shigenori Tomiyama
Applying Cuckoo Hashing for FPGA-based Pattern Matching in NIDS/NIPS. FPT (2007)
Thinh Ngoc Tran, Surin Kittitornkun
FPGA-Based Cuckoo Hashing for Pattern Matching in NIDS/NIPS. APNOMS (2007)
Thinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama
Manifold similarity search of DNA sequences with reconfigurable hardware. FPGA (2006)
Kridsadakorn Chaichoompu, Surin Kittitornkun, Sissades Tongsima
MT-ClustalW: multithreading multiple sequence alignment. IPDPS (2006)
Surin Kittitornkun, Yu Hen Hu
Supersystolic arrays on large-scale FPGA structures. ISCAS (2) (2003)
Surin Kittitornkun, Yu Hen Hu
Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures. IEEE Trans. Very Large Scale Integr. Syst. 11 (2) (2003)
Surin Kittitornkun, Yu Hen Hu
Processor Array Synthesis from Shift-Variant Deep Nested Do Loops. J. Supercomput. 24 (3) (2003)
Surin Kittitornkun, Yu Hen Hu
Efficient Implementation of Nested-Loop Multimedia Algorithms. EURASIP J. Adv. Signal Process. 2001 (3) (2001)
Surin Kittitornkun, Yu Hen Hu
Frame-level pipelined motion estimation array processor. IEEE Trans. Circuits Syst. Video Technol. 11 (2) (2001)
Seungjoon Yang, Surin Kittitornkun, Yu Hen Hu, Truong Q. Nguyen, Damon L. Tull
Low bit rate video sequence coding artifact removal. MMSP (2001)
Adam H. Li, Surin Kittitornkun, Yu Hen Hu, Dong-Seek Park, John D. Villasenor
Data Partitioning and Reversible Variable Length Codes for Robust Video Communications. Data Compression Conference (2000)
Seungjoon Yang, Surin Kittitornkun, Yu Hen Hu, Truong Q. Nguyen, Damon L. Tull
Blocking Artifact Free Inverse Discrete Cosine Transform. ICIP (2000)