Sung-En Hsieh

Publication Activity (10 Years)

Years Active: 2015-2023
Publications (10 Years): 12

Top Topics

Synthetic Aperture Radar

Analog To Digital Converter

Top Venues

IEEE J. Solid State Circuits

Publications

Sung-En Hsieh, Chun-Hao Wei, Cheng-Xin Xue, Hung-Wei Lin, Wei-Hsuan Tu, En-Jui Chang, Kai-Taing Yang, Po-Heng Chen, Wei-Nan Liao, Li Lian Low, Chia-Da Lee, Allen-CL Lu, Jenwei Liang, Chih-Chung Cheng, Tzung-Hung Kang
A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation. ISSCC (2023)
Sung-En Hsieh, Tzu-Chien Wu, Chun-Chih Hou
A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations. ISSCC (2023)
Sung-En Hsieh, Chih-Cheng Hsieh
A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator. IEEE J. Solid State Circuits 54 (6) (2019)
Sung-En Hsieh, Chih-Cheng Hsieh
A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC. IEEE J. Solid State Circuits 53 (9) (2018)
Sung-En Hsieh, Chen-Che Kao, Chih-Cheng Hsieh
A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization. IEEE J. Solid State Circuits 53 (10) (2018)
Sung-En Hsieh, Chih-Cheng Hsieh
A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator. ISSCC (2018)
Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, Chih-Cheng Hsieh
A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections. A-SSCC (2018)
Chen-Che Kao, Sung-En Hsieh, Chih-Cheng Hsieh
A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization. A-SSCC (2017)
Sung-En Hsieh, Chih-Cheng Hsieh
A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS. ISCAS (2016)
Albert Yen-Chih Chiou, Sung-En Hsieh, Yan-Quan Pan, Chia-Chi Kuo, Chih-Cheng Hsieh
An integrated CMOS optical sensing chip for multiple bio-signal detections. A-SSCC (2016)
Sung-En Hsieh, Chih-Cheng Hsieh
A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (12) (2016)
Sung-En Hsieh, Chih-Cheng Hsieh
A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC. VLSI Circuits (2016)
Sung-En Hsieh, Cheng-Kang Ho, Chih-Cheng Hsieh
A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter. ISCAS (2015)