A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS.

Sung-En Hsieh Chih-Cheng Hsieh

Published in: ISCAS (2016)

Keyphrases

analog to digital converter
successive approximation
synthetic aperture radar
power consumption
high speed
protection scheme
nm technology
post processing
low cost
sar images
power supply
circuit design
pseudorandom
cmos technology
delay insensitive
analog vlsi
image reconstruction
bit string