A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC.

Sung-En Hsieh Chih-Cheng Hsieh

Published in: VLSI Circuits (2016)

Keyphrases

synthetic aperture radar
databases
preprocessing step
artificial intelligence
post processing
parameter estimation
image reconstruction
max csp
real time
information systems
multiresolution