A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations.

Sung-En Hsieh Tzu-Chien Wu Chun-Chih Hou

Published in: ISSCC (2023)

Keyphrases

power consumption
high speed
lower bound
random sampling
clock frequency
linear programming
semidefinite
buffer size
neural network
sample size
monte carlo
reference frame
sampling methods
parallel architecture