Saleh Abdel-Hafeez

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 9

Top Topics

Communication Systems

Metal Oxide Semiconductor

Memory Management

Reconfigurable Architecture

Top Venues

Int. J. Circuit Theory Appl.

Circuits Syst. Signal Process.

IET Comput. Digit. Tech.

Comput. Electr. Eng.

Publications

Saleh Abdel-Hafeez
A fast and cost-effective integer restoring division hardware. Comput. Electr. Eng. 116 (2024)
Saleh Abdel-Hafeez, Shadi M. Harb
A novel self-timing CMOS first-edge take-all circuit for on-chip communication systems. IET Comput. Digit. Tech. 17 (3-4) (2023)
Saleh Abdel-Hafeez
Programmable Feedback Shift Register. Circuits Syst. Signal Process. 42 (8) (2023)
Saleh Abdel-Hafeez, Sanabel Otoom, Muhannad Quwaider
Design of memory Alias Table based on the SRAM 8T-Cell. Int. J. Circuit Theory Appl. 50 (8) (2022)
Saleh Abdel-Hafeez, Ann Gordon-Ross
Reconfigurable FIFO memory circuit for synchronous and asynchronous communication. Int. J. Circuit Theory Appl. 49 (4) (2021)
Ann Gordon-Ross, Saleh Abdel-Hafeez, Mohamad Hammam Alsafrjalani
A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems. ISVLSI (2019)
Saleh Abdel-Hafeez, Ann Gordon-Ross, Samer Abubaker
A comparison-free sorting algorithm on CPUs and GPUs. J. Supercomput. 74 (11) (2018)
Saleh Abdel-Hafeez, Ali M. Shatnawi
High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder. Circuits Syst. Signal Process. 37 (6) (2018)
Saleh Abdel-Hafeez, Ann Gordon-Ross
An Efficient O(N) Comparison-Free Sorting Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 25 (6) (2017)
Saleh Abdel-Hafeez, Ann Gordon-Ross, Behrooz Parhami
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree. IEEE Trans. Very Large Scale Integr. Syst. 21 (11) (2013)
Saleh Abdel-Hafeez, Mohammad Shatnawi, Ann Gordon-Ross
A double data rate 8T-cell SRAM architecture for systems-on-chip. ISSoC (2012)
Saleh Abdel-Hafeez, Ann Gordon-Ross
Frequency Divider Based on a State Look-Ahead Structure. Circuits Syst. Signal Process. 30 (6) (2011)
Saleh Abdel-Hafeez, Ann Gordon-Ross
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic. IEEE Trans. Very Large Scale Integr. Syst. 19 (6) (2011)
Saleh Abdel-Hafeez, Ann Gordon-Ross, Asem Albosul, Ahmad Shatnawi, Shadi M. Harb
A Shadow Dynamic Finite State Machine for Branch Prediction: An Alternative for the 2-bit Saturating Counter. Informatica (Slovenia) 35 (2) (2011)
Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt
High speed digital CMOS divide-by-N fequency divider. ISCAS (2008)
Saleh Abdel-Hafeez, Anas S. Matalkah
CMOS Eight-Transistor Memory Cell for Low-Dynamic-Power High-Speed Embedded SRAM. J. Circuits Syst. Comput. 17 (5) (2008)
Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt
Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports. PATMOS (2007)
Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt
A low-power CAM using a 12-transistor design cell. VLSI-SoC (2007)
Saleh Abdel-Hafeez, Shadi M. Harb
A VLSI High-Performance Priority Encoder Using Standard CMOS Library. IEEE Trans. Circuits Syst. II Express Briefs (8) (2006)