Reconfigurable FIFO memory circuit for synchronous and asynchronous communication.
Saleh Abdel-HafeezAnn Gordon-RossPublished in: Int. J. Circuit Theory Appl. (2021)
Keyphrases
- high speed
- memory requirements
- interprocess communication
- communication networks
- computing power
- power reduction
- data acquisition
- memory usage
- memory size
- general purpose
- computer networks
- computational power
- reconfigurable architecture
- delay insensitive
- power dissipation
- communication protocol
- communication overhead
- communication technologies
- low power
- low cost