Saied Hemati

Publication Activity (10 Years)

Years Active: 2003-2020
Publications (10 Years): 10

Top Topics

Error Correction

Health Monitoring

Top Venues

IEEE Trans. Commun.

IEEE Trans. Signal Process.

Publications

Niloofar Hezarjaribi, Zhila Esna Ashari, James F. Frenzel, Hassan Ghasemzadeh, Saied Hemati
Personality Assessment from Text for Machine Commonsense Reasoning. CoRR (2020)
Niloofar Hezarjaribi, Sepideh Mazrouee, Saied Hemati, Naomi Chaytor, Martine Perrigue, Hassan Ghasemzadeh
Human-in-the-loop Learning for Personalized Diet Monitoring from Unstructured Mobile Data. ACM Trans. Interact. Intell. Syst. 9 (4) (2019)
Hossein Mani, Saied Hemati
Symbol-Level Stochastic Chase Decoding of Reed-Solomon and BCH Codes. IEEE Trans. Commun. 67 (8) (2019)
Andrew J. Wong, Saied Hemati, Warren J. Gross
A Modular Architecture for Structured Long Block-Length LDPC Decoders. J. Signal Process. Syst. 90 (1) (2018)
Saied Hemati
Dynamics of ML Approaching Randomized Decoders on Graphs with Cycles. MWSCAS (2018)
Parviz Khaledian, Brian K. Johnson, Saied Hemati
Power Grid Resiliency Improvement Through Remedial Action Schemes. IECON (2018)
Hossein Mani, Saied Hemati
Symbolic Stochastic Chase Decoding of Reed-Solomon and BCH Codes. CoRR (2017)
Saied Hemati, François Leduc-Primeau, Warren J. Gross
A Relaxed Min-Sum LDPC Decoder With Simplified Check Nodes. IEEE Commun. Lett. 20 (3) (2016)
Saied Hemati, Sepideh Rahmani
Exploiting dental implants for creating wired implantable health monitoring devices. HealthCom (2016)
Saied Hemati
Mitigating hardware cyber-security risks in error correcting decoders. ISTC (2016)
Andrew J. Wong, Saied Hemati, Warren J. Gross
Efficient implementation of structured long block-length LDPC codes. ASAP (2015)
Saied Hemati
Mitigating Hardware Cyber-Security Risks in Error Correcting Decoders. CoRR (2015)
Kevin Cushon, Saied Hemati, Camille Leroux, Shie Mannor, Warren J. Gross
High-Throughput Energy-Efficient LDPC Decoders Using Differential Binary Message Passing. IEEE Trans. Signal Process. 62 (3) (2014)
Kevin Cushon, Saied Hemati, Shie Mannor, Warren J. Gross
Energy-efficient gear-shift LDPC decoders. ASAP (2014)
Gabi Sarkis, Saied Hemati, Shie Mannor, Warren J. Gross
Stochastic Decoding of LDPC Codes over GF(q). IEEE Trans. Commun. 61 (3) (2013)
Alexandru Ciobanu, Saied Hemati, Warren J. Gross
Adaptive Multiset Stochastic Decoding of Non-Binary LDPC Codes. IEEE Trans. Signal Process. 61 (16) (2013)
François Leduc-Primeau, Saied Hemati, Shie Mannor, Warren J. Gross
Relaxed Half-Stochastic Belief Propagation. IEEE Trans. Commun. 61 (5) (2013)
Guanghua He, Gabi Sarkis, Saied Hemati, Warren J. Gross, Baoming Bai
Low-Complexity Channel-Likelihood Estimation for Non-Binary Codes and QAM. IEEE Commun. Lett. 16 (6) (2012)
Romain Heloir, Camille Leroux, Saied Hemati, Matthieu Arzel, Warren J. Gross
Stochastic chase decoder for reed-solomon codes. NEWCAS (2012)
François Leduc-Primeau, Saied Hemati, Shie Mannor, Warren J. Gross
Relaxed Half-Stochastic Belief Propagation CoRR (2012)
François Leduc-Primeau, Saied Hemati, Shie Mannor, Warren J. Gross
Dithered Belief Propagation Decoding. IEEE Trans. Commun. 60 (8) (2012)
Camille Leroux, Saied Hemati, Shie Mannor, Warren J. Gross
Stochastic Chase Decoding of Reed-Solomon Codes. IEEE Commun. Lett. 14 (9) (2010)
Saeed Sharifi Tehrani, Ali Naderi, Guy-Armand Kamendje, Saied Hemati, Shie Mannor, Warren J. Gross
Majority-based tracking forecast memories for stochastic LDPC decoding. IEEE Trans. Signal Process. 58 (9) (2010)
Kevin Cushon, Camille Leroux, Saied Hemati, Shie Mannor, Warren J. Gross
A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding. IEEE Trans. Circuits Syst. II Express Briefs (11) (2010)
François Leduc-Primeau, Saied Hemati, Shie Mannor, Warren J. Gross
Lowering Error Floors Using Dithered Belief Propagation. GLOBECOM (2010)
Gabi Sarkis, Saied Hemati, Shie Mannor, Warren J. Gross
Relaxed half-stochastic decoding of LDPC codes over GF(q). Allerton (2010)
Saied Hemati, Abbas Yongaçoglu
Dynamics of analog decoders for different message representation domains. IEEE Trans. Commun. 58 (3) (2010)
Saied Hemati, Abbas Yongaçoglu
On the Dynamics of Analog Min-Sum Iterative Decoders: An Analytical Approach. IEEE Trans. Commun. 58 (8) (2010)
Nastaran Mobini, Amir H. Banihashemi, Saied Hemati
A differential binary message-passing LDPC decoder. IEEE Trans. Commun. 57 (9) (2009)
François Leduc-Primeau, Saied Hemati, Warren J. Gross, Shie Mannor
A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes. GLOBECOM (2009)
Saied Hemati, Abbas Yongaçoglu
On the Dynamics of Analog Min-Sum Iterative Decoders, an Analytical Approach. ISIT (2007)
Nastaran Mobini, Amir H. Banihashemi, Saied Hemati
A Differential Binary Message-Passing LDPC Decoder. GLOBECOM (2007)
Saied Hemati, Amir H. Banihashemi
Convergence Speed and Throughput of Analog Decoders. IEEE Trans. Commun. 55 (5) (2007)
Saied Hemati, Amir H. Banihashemi, Calvin Plett
A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32, 8) Low-Density Parity-Check (LDPC) Code. IEEE J. Solid State Circuits 41 (11) (2006)
Saied Hemati, Amir H. Banihashemi
Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes. IEEE Trans. Commun. 54 (1) (2006)
Saied Hemati, Amir H. Banihashemi, Calvin Plett
An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32, 8, 10) LDPC code. CICC (2005)
Saied Hemati, Amir H. Banihashemi, Calvin Plett
A high-speed analog min-sum iterative decoder. ISIT (2005)
Saied Hemati, Amir H. Banihashemi
On the dynamics of continuous-time analog iterative decoding. ISIT (2004)
Mohammadreza Yazdani, Saied Hemati, Amir H. Banihashemi
Improving belief propagation on graphs with cycles. IEEE Commun. Lett. 8 (1) (2004)
Saied Hemati, Amir H. Banihashemi
Comparison between continuous-time asynchronous and discrete-time synchronous iterative decoding. GLOBECOM (2004)
Saied Hemati, Amir H. Banihashemi
Iterative decoding in analog CMOS. ACM Great Lakes Symposium on VLSI (2003)
Saied Hemati, Amir H. Banihashemi
A current mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders. ICECS (2003)