An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32, 8, 10) LDPC code.
Saied HematiAmir H. BanihashemiCalvin PlettPublished in: CICC (2005)
Keyphrases
- low density parity check
- ldpc codes
- analog vlsi
- min sum
- vlsi architecture
- decoding algorithm
- low power
- error correction
- circuit design
- turbo codes
- message passing
- distributed video coding
- channel coding
- successive approximation
- distributed source coding
- focal plane
- lower bound
- rate allocation
- floating gate
- analog to digital converter
- low complexity
- power consumption
- np hard
- error resilience
- computational complexity
- image sequences
- video transmission