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A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32, 8) Low-Density Parity-Check (LDPC) Code.
Saied Hemati
Amir H. Banihashemi
Calvin Plett
Published in:
IEEE J. Solid State Circuits (2006)
Keyphrases
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low density parity check
ldpc codes
vlsi architecture
min sum
low power
decoding algorithm
error correction
channel coding
distributed video coding
low complexity
high speed
power consumption
lower bound
message passing
physical layer
np hard
vlsi implementation
turbo codes
image transmission
error resilience