Sachin Maheshwari

Publication Activity (10 Years)

Years Active: 2007-2023
Publications (10 Years): 19

Top Topics

Rapidly Evolving

Quantum Mechanics

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Sachin Maheshwari, Jiaqi Wang, Alexander Serb, Themistoklis Prodromakis
A Memristor-based Tuneable Offset Comparator. NEWCAS (2023)
Andrea Mifsud, Jiawei Shen, Peilong Feng, Lijie Xie, Chaohan Wang, Yihan Pan, Sachin Maheshwari, Shady Agwa, Spyros Stathopoulos, Shiwei Wang, Alexander Serb, Christos Papavassiliou, Themis Prodromakis, Timothy G. Constandinou
A CMOS-based Characterisation Platform for Emerging RRAM Technologies. CoRR (2022)
Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis
An Adiabatic Capacitive Artificial Neuron with RRAM-based Threshold Detection for Energy-Efficient Neuromorphic Computing. CoRR (2022)
Andrea Mifsud, Jiawei Shen, Peilong Feng, Lijie Xie, Chaohan Wang, Yihan Pan, Sachin Maheshwari, Shady Agwa, Spyros Stathopoulos, Shiwei Wang, Alexander Serb, Christos Papavassiliou, Themis Prodromakis, Timothy G. Constandinou
A CMOS-based Characterisation Platform for Emerging RRAM Technologies. ISCAS (2022)
Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis
An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (9) (2022)
Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis
Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (12) (2021)
Sachin Maheshwari, Viv A. Bartlett, Izzet Kale
A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (8) (2021)
Jiaqi Wang, Alexantrou Serb, Christos Papavassiliou, Sachin Maheshwari, Themis Prodromakis
Analysing and measuring the performance of memristive integrating amplifiers. Int. J. Circuit Theory Appl. 49 (11) (2021)
Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis
Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (12) (2021)
Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis
An Adiabatic Regenerative Capacitive Artificial Neuron. ISCAS (2021)
Jiaqi Wang, Alexander Serb, Christos Papavassiliou, Sachin Maheshwari, Themistoklis Prodromakis
Analysing and Measuring the Performance ofMemristive Integrating Amplifiers. CoRR (2020)
Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Lieuwe B. Leene, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis
Hybrid CMOS/Memristor Circuit Design Methodology. CoRR (2020)
Brijpal Singh, Zahid A. Khan, Arshad Noor Siddiquee, Sachin Maheshwari
Optimal design of flux for submerged arc weld properties based on RSM coupled with GRA and PCA. Int. J. Manuf. Technol. Manag. 34 (1) (2020)
Sachin Maheshwari, Izzet Kale
Adiabatic Implementation of Manchester Encoding for Passive NFC System. DATE (2019)
Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale
Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach. Integr. 67 (2019)
Sachin Maheshwari, Izzet Kale
Impact of Adiabatic Logic Families on the Power-Clock Generator Energy Efficiency. PRIME (2019)
Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale
VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design. PATMOS (2018)
Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale
Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication. Integr. 62 (2018)
Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale
Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers. ECCTD (2017)
Sachin Maheshwari, Jimit Patel, Sumit K. Nirmalkar, Anu Gupta
Logical effort based power-delay-product optimization. ICACCI (2014)
Sachin Maheshwari, Rameez Raza, Pramod Kumar, Anu Gupta
Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology. VDAT (2013)
Himadri Singh Raghav, Sachin Maheshwari, B. Prasad Singh
Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology. VDAT (2013)
Sachin Maheshwari, Himadri Singh Raghav, Anu Gupta
Characterization of Logical Effort for Improved Delay. VDAT (2013)
Pushpendrai Singh Bharti, Sachin Maheshwari, Chitra Sharma
Neural-Network- Based Modeling of Electric Discharge Machining Process. SOCO (2011)
Shankar Singh, Sachin Maheshwari, Aloke Dey, Poorn Chandra Pandey
Experimental results and analysis for Electrical Discharge Machining (EDM) of aluminium metal matrix composites with powder-mixed dielectric: Lenth's method. Int. J. Manuf. Technol. Manag. 21 (1/2) (2010)
Shankar Singh, Sachin Maheshwari, Poorn Chandra Pandey
Optimisation of multiperformance characteristics in electric discharge machining of Aluminium Matrix Composites (AMCs) using Taguchi DOE methodology. Int. J. Manuf. Res. 2 (2) (2007)