Rushik Parmar

Publication Activity (10 Years)

Years Active: 2022-2024
Publications (10 Years): 8

Top Topics

Symmetric Matrices

Vlsi Architecture

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

RADIOELEKTRONIKA

Publications

Rushik Parmar, Khushil Yadav, Gauraangi Anand, Gaurav Trivedi
An SNN-Inspired Area- and Power-Efficient VLSI Architecture of Myocardial Infarction Classifier for Wearable Devices. IEEE Trans. Circuits Syst. II Express Briefs 71 (6) (2024)
Bipul Boro, Rushik Parmar, Ashvinikumar Dongre, Gaurav Trivedi
Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing. ISQED (2024)
Rushik Parmar, Meenali Janveja, Jan Pidanic, Gaurav Trivedi
Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices. IEEE Trans. Very Large Scale Integr. Syst. 31 (3) (2023)
Meenali Janveja, Rushik Parmar, Gaurav Trivedi
MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier for Wearable Healthcare Applications. IEEE Trans. Circuits Syst. II Express Briefs 70 (3) (2023)
Bipul Boro, Ashvinikumar Dongre, Rushik Parmar, Gaurav Trivedi
Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing. APCCAS (2023)
Meenali Janveja, Rushik Parmar, Gaurav Trivedi, Jan Pidanic, Zdenek Nemec
An Energy Efficient and Resource Optimal VLSI Architecture for ECG Feature Extraction for Wearable Healthcare Applications. RADIOELEKTRONIKA (2022)
Rushik Parmar, Meenali Janveja, Gaurav Trivedi, Jan Pidanic, Zdenek Nemec
An Area and Power Efficient VLSI Architecture to Detect Obstructive Sleep Apnea for Wearable Devices. RADIOELEKTRONIKA (2022)
Meenali Janveja, Rushik Parmar, Mayank Tantuway, Gaurav Trivedi
A DNN-Based Low Power ECG Co-Processor Architecture to Classify Cardiac Arrhythmia for Wearable Devices. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)