A DNN-Based Low Power ECG Co-Processor Architecture to Classify Cardiac Arrhythmia for Wearable Devices.
Meenali JanvejaRushik ParmarMayank TantuwayGaurav TrivediPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2022)
Keyphrases
- low power
- ecg signals
- high speed
- single chip
- wearable devices
- heart rate variability
- vlsi architecture
- low cost
- power consumption
- cardiac arrhythmias
- gate array
- mit bih arrhythmia database
- cmos technology
- nm technology
- mixed signal
- heart rate
- heart disease
- logic circuits
- real time
- image sensor
- beat classification
- low power consumption
- parallel processing
- super resolution
- frame rate
- power reduction
- data flow
- power dissipation