Rainer G. Spallek

Publication Activity (10 Years)

Years Active: 1997-2020
Publications (10 Years): 10

Top Topics

Reconfigurable Hardware

Procrustes Analysis

Top Venues

GI-Jahrestagung

Publications

Mohammed Bawatna, Oliver Knodel, Rainer G. Spallek
Real-Time Data Compression System for Data-Intensive Scientific Applications Using FPGA Architecture. CSOC (3) (2020)
Mohammed Bawatna, Oliver Knodel, Rainer G. Spallek
Possibilities and Challenges for Reconfigurable Hardware and Cloud Architectures in Data-Intensive Scientific Applications. SDS (2020)
Mohammed Bawatna, Bertram Green, Sergey Kovalev, Jan-Christoph Deinert, Oliver Knodel, Rainer G. Spallek
Research and Implementation of Efficient Parallel Processing of Big Data at TELBE User Facility. SPECTS (2019)
Mohammed Bawatna, Bertram Green, Sergey Kovalev, Jan-Christoph Deinert, Oliver Knodel, Rainer G. Spallek
Research and implementation of efficient parallel processing of big data at TELBE user facility. SummerSim (2019)
Oliver Knodel, Steffen Köhler, Marko Rößler, Rainer G. Spallek
First Workshop on Hardware Defined Programming - HDP. GI-Jahrestagung (2017)
Steffen Köhler, Rainer G. Spallek
Modellierung anwendungsspezifischer Hardware und deren Einbettung in die DBT-basierte Prozessor-Verhaltenssimulation. GI-Jahrestagung (2017)
Paul R. Genßler, Oliver Knodel, Rainer G. Spallek
A New Level of Trusted Cloud Computing - Virtualized Reconfigurable Resources in a Security-First Architecture. GI-Jahrestagung (2017)
Oliver Knodel, Patrick Lehmann, Rainer G. Spallek
RC3E: Reconfigurable Accelerators in Data Centres and Their Provision by Adapted Service Models. CLOUD (2016)
Thomas B. Preußer, Martin Zabel, Patrick Lehmann, Rainer G. Spallek
The portable open-source IP core and utility library PoC. ReConFig (2016)
Oliver Knodel, Paul R. Genssler, Rainer G. Spallek
Migration of long-running Tasks between Reconfigurable Resources using Virtualization. SIGARCH Comput. Archit. News 44 (4) (2016)
Oliver Knodel, Rainer G. Spallek
Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud. DSD (2015)
Kai-Uwe Irrgang, Thomas B. Preußer, Rainer G. Spallek
Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wörterbuchansatz. GI-Jahrestagung (2015)
Oliver Knodel, Rainer G. Spallek
RC3E: Provision and Management of Reconfigurable Hardware Accelerators in a Cloud Environment. CoRR (2015)
Oliver Knodel, Martin Zabel, Patrick Lehmann, Rainer G. Spallek
Educating hardware design - From primary school children to postgraduate engineers. FPL (2014)
Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek
PoC-align: An open-source alignment accelerator using FPGAs. ReConFig (2014)
Thomas B. Preußer, Rainer G. Spallek
Ready PCIe data streaming solutions for FPGAs. FPL (2014)
Oliver Knodel, Andy Georgi, Patrick Lehmann, Wolfgang E. Nagel, Rainer G. Spallek
Integration of a Highly Scalable, Multi-FPGA-Based Hardware Accelerator in Common Cluster Infrastructures. ICPP (2013)
Patrick Lehmann, Thomas Frank, Oliver Knodel, Steffen Köhler, Thomas B. Preußer, Rainer G. Spallek
Weasel: A platform-independent streaming-optimized SATA controller. FPL (2013)
Marco Kaufmann, Rainer G. Spallek
Superblock compilation and other optimization techniques for a Java-based DPT machine emulator. VEE (2013)
Oliver Knodel, Rainer G. Spallek
Integration of a multi-FPGA system in a common cluster environment. FPL (2013)
Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek
Short-Read Mapping by a Systolic Custom FPGA Computation. FCCM (2012)
Martin Zabel, Thomas B. Preußer, Rainer G. Spallek
Increasing the efficiency of an embedded multi-core bytecode processor using an object cache. JTRES (2012)
Kai-Uwe Irrgang, Rainer G. Spallek
Comparison of Trace-Port-Designs for On-Chip-Instruction-Trace. IEEE GSC (2012)
Thomas B. Preußer, Martin Zabel, Rainer G. Spallek
Accelerating Computations on FPGA Carry Chains by Operand Compaction. IEEE Symposium on Computer Arithmetic (2011)
Oliver Knodel, Thomas B. Preußer, Rainer G. Spallek
Next-generation massively parallel short-read mapping on FPGAs. ASAP (2011)
Marco Kaufmann, Matthias Häsing, Thomas Preußer, Rainer G. Spallek
The Java Virtual Machine in retargetable, high-performance instruction set simulation. PPPJ (2011)
Thomas B. Preußer, Rainer G. Spallek
Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains. FPL (2010)
Michael Dittrich, Thomas B. Preußer, Rainer G. Spallek
Solving Sudokus through an incidence matrix on an FPGA. FPT (2010)
Martin Zabel, Rainer G. Spallek
Application requirements and efficiency of embedded Java bytecode multi-cores. JTRES (2010)
Thomas B. Preußer, Peter Reichel, Rainer G. Spallek
An Embedded GC Module with Support for Multiple Mutators and Weak References. ARCS (2010)
Jens Braunes, Rainer G. Spallek
Generating the trace qualification configuration for MCDS from a high level language. DATE (2009)
Martin Zabel, Thomas B. Preußer, Rainer G. Spallek
High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation. MBMV (2009)
Thomas B. Preußer, Rainer G. Spallek
Mapping basic prefix computations to fast carry-chain structures. FPL (2009)
Thomas Preußer, Rainer G. Spallek
Java-Programmed Bootloading in Spite of Load-Time Code Patching on a Minimal Embedded Bytecode Processor. ESA (2008)
Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek
Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. ARC (2008)
Thomas Preußer, Martin Zabel, Rainer G. Spallek
Enabling constant-time interface method dispatch in embedded Java processors. JTRES (2007)
Martin Zabel, Thomas B. Preußer, Peter Reichel, Rainer G. Spallek
Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. DSD (2007)
Thomas Preußer, Martin Zabel, Rainer G. Spallek
Bump-pointer method caching for embedded Java processors. JTRES (2007)
Jörg Schneider, Marcel Naggatz, Rainer G. Spallek
Implementation of Architecture Concepts for Hardware Agent Systems. CIT (2007)
Steffen Köhler, Martin Zimmerling, Martin Zabel, Rainer G. Spallek
Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures. ARCS Workshops (2006)
Thomas B. Preußer, Rainer G. Spallek
Analysis of a Fully-Scalable Digital Fractional Clock Divider. ASAP (2006)
Jens Braunes, Rainer G. Spallek
A Compiler-Oriented Architecture Description for Reconfigurable Systems. ARC (2006)
Jens Braunes, Steffen Köhler, Annett Königsmann, Rainer G. Spallek
Ein Zwischenformat-Profiler für das RECAST-Framework. ARCS Workshops (2005)
Martin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek
Design space exploration of coarse-grain reconfigurable DSPs. ReConFig (2005)
Jens Braunes, Steffen Köhler, Rainer G. Spallek
RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures. ARCS (2004)
Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek
Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. FPL (2004)
Thomas Preußer, Steffen Köhler, Rainer G. Spallek
RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing. ESA/VLSI (2004)
Sergej Sawitzki, Rainer G. Spallek
Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. FPL (2003)
Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek
Improving Code Efficiency for Reconfigurable VLIW Processors. IPDPS (2002)
Sebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus Künanz
A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor. FPL (2002)
Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek
Prototyping Framework for Reconfigurable Processors. FPL (2001)
Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek, Jörg Schneider, S. Rülke
Experimenteller Vergleich verschiedener Entwurfsmethoden für FPGA-basierte Entwurfsabläufe. MBMV (2000)
Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube
Formal Verification of a Reconfigurable Microprocessor. FPL (2000)
Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube
Formal Verification for Microprocessors with Extendable Instruction Set. ASAP (2000)
Steffen Köhler, Sergej Sawitzki, Achim Gratz, Rainer G. Spallek
Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic. IPPS/SPDP Workshops (1999)
Sergej Sawitzki, Rainer G. Spallek
A Concept for an Evaluation Framework for Reconfigurable Systems. FPL (1999)
Raimar Falke, Michael Peter, Achim Gratz, Rainer G. Spallek
Common Logging Interface - Ein System zum Sammeln und Verarbeiten von Debugnachrichten in verteilten Umgebungen. Java-Informations-Tage (1998)
Sergej Sawitzki, Achim Gratz, Rainer G. Spallek
Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. FPL (1998)
Achim Gratz, Rainer G. Spallek
Bewertung von modernen Rechnerarchitekturen hinsichtlich numerischer Simulationen auf heterogenen Plattformen. MMB (Kurzbeiträge) (1997)
Gert Markwardt, Günter Kemnitz, Rainer G. Spallek
A RISC Processor with Extended Forwarding. ARCS (1997)