Puneet Sareen

Publication Activity (10 Years)

Years Active: 2010-2017
Publications (10 Years): 2

Top Topics

Metal Oxide Semiconductor

Object Tracking

Particle Filtering

Top Venues

Publications

Jens Anders, Sebastian Bader, Markus Dietl, Puneet Sareen, G. Rombach, S. Tambouris, Maurits Ortmanns
A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS. A-SSCC (2017)
S. Fahmy, Markus Dietl, Puneet Sareen, Maurits Ortmanns, Jens Anders
A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter. NORCAS (2015)
Mitesh Yogesh, Puneet Sareen, Markus Dietl, Ketan Dewan
A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter. NORCHIP (2012)
Markus Dietl, Puneet Sareen
A new low power and area efficient semi-digital PLL architecture for low bandwidth applications. ACM Great Lakes Symposium on VLSI (2011)
Vivek Elangovan, Markus Dietl, Puneet Sareen
Very high bandwidth semi-digital PLL with large operating frequency range. NORCHIP (2011)
Markus Dietl, Puneet Sareen
Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance. NESEA (2010)