Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance.

Markus Dietl Puneet Sareen

Published in: NESEA (2010)

Keyphrases

coding scheme
low power
high speed
mixed signal
power consumption
low cost
deblocking filter
digital signal processing
cmos technology
power dissipation
computational complexity
wavelet transform
image sensor
delay insensitive