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A new low power and area efficient semi-digital PLL architecture for low bandwidth applications.
Markus Dietl
Puneet Sareen
Published in:
ACM Great Lakes Symposium on VLSI (2011)
Keyphrases
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low power
mixed signal
low bandwidth
vlsi architecture
low cost
power consumption
high speed
cmos technology
wireless networks
video conferencing
real time
mobile devices
highly efficient