Peter M. Maurer

Publication Activity (10 Years)

Years Active: 1983-2024
Publications (10 Years): 11

Top Topics

Symmetry Detection

Simulation Environment

Top Venues

SpringSim (TMS-DEVS)

Publications

Peter M. Maurer
Discrete random variates with finite support using differential search trees. Simul. 100 (8) (2024)
Peter M. Maurer
DGL Version 2 - Random Testing in the Mobile Computing Era. SDSC (2023)
Peter M. Maurer, John Carbone
Generating Random XML Files Using DGL. CSCI (2022)
Peter M. Maurer
Teaching Induction and Deductive Reasoning. CSCI (2022)
Peter M. Maurer
Massive Generation of Data with Random Variates. ANNSIM (2021)
Peter M. Maurer
Computer Science Theory from a Practical Point of View. CSCI (2021)
Peter M. Maurer
A nominal/inertial delay metamorphic differential simulator. SummerSim (2019)
Peter M. Maurer
Finite random variates using differential search trees. SummerSim (2017)
Peter M. Maurer
Time-parallel multi-delay logic simulation. SpringSim (TMS-DEVS) (2016)
Peter M. Maurer
A second look at oblivious simulation. SummerSim (2015)
Peter M. Maurer
Levelized compiled code multi-delay logic simulation. SpringSim (TMS-DEVS) (2015)
Peter M. Maurer
A universal symmetry detection algorithm. DATE (2014)
Peter M. Maurer
Metamorphic differential simulation using the multi-delay timing model. SpringSim (TMS-DEVS) (2013)
Peter M. Maurer
Extending symmetric variable-pair transitivities using state-space transformations. ACM Great Lakes Symposium on VLSI (2012)
Peter M. Maurer
Conjugate symmetry. Formal Methods Syst. Des. 38 (3) (2011)
Peter M. Maurer
Using conjugate symmetries to enhance gate-level simulations. DATE (2006)
Peter M. Maurer
Converting command-line applications into binary components. Softw. Pract. Exp. 35 (8) (2005)
William B. Poucher, Peter M. Maurer
How to Make Program Assessment Work for You. FECS (2005)
Peter M. Maurer
Metamorphic Programming: Unconventional High Performance. Computer 37 (3) (2004)
Sandeep K. Kondapuram, Peter M. Maurer
Random Characterization of Design Automation Algorithms. ISVLSI (2003)
Peter M. Maurer
Efficient event-driven simulation by exploiting the output observability of gate clusters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (11) (2003)
Allen S. Parrish, Joe Hollingsworth, Peter M. Maurer, Benjamin Shults, Bruce W. Weide
Identifying an appropriate view of software components for undergraduate education. SIGCSE (2001)
Peter M. Maurer
Logic Simulation Using Networks of State Machines. DATE (2000)
Peter M. Maurer
Components: What If They Gave a Revolution and Nobody Came? Computer 33 (6) (2000)
Peter M. Maurer
Event Driven Simulation Without Loops or Conditionals. ICCAD (2000)
Peter M. Maurer, William J. Schilp
State-Machine Based Logic Simulation Using Three Logic Values. VLSI Design (2000)
Peter M. Maurer, William J. Schilp
Software Bit-Slicing: A Technique for Improving Simulation Performance. DATE (1999)
Peter M. Maurer
Efficient Simulation for Hierarchical and Partitioned Circuits. VLSI Design (1999)
Peter M. Maurer
The inversion algorithm for digital simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (7) (1997)
Yun Sik Lee, Peter M. Maurer
Bit-parallel multidelay simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (12) (1996)
Peter M. Maurer
Is Compiled Simulation Really Faster than Interpreted Simulation? VLSI Design (1996)
William J. Schilp, Peter M. Maurer
Unit delay simulation with the inversion algorithm. ICCAD (1996)
Peter M. Maurer, Yun Sik Lee
Gateways: a technique for adding event-driven behavior to compiled simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (3) (1994)
Peter M. Maurer
The Inversion Algorithm for digital simulation. ICCAD (1994)
Peter M. Maurer
The shadow algorithm: a scheduling technique for both compiled and interpreted simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (9) (1993)
Yun Sik Lee, Peter M. Maurer
Parallel multi-delay simulation. ICCAD (1993)
Peter M. Maurer
The Design and Implementation of a Grammar-based Data Generator. Softw. Pract. Exp. 22 (3) (1992)
Peter M. Maurer
Two new techniques for unit-delay compiled simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (9) (1992)
Yun Sik Lee, Peter M. Maurer
Two New Techniques for Compiled Multi-Delay Logic Simulation. DAC (1992)
Peter M. Maurer
Scheduling blocks of hierarchical compiled simulation of combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (2) (1991)
Peter M. Maurer, Craig D. Morency
The FHDL PLA tools. ACM Southeast Regional Conference (1990)
Peter M. Maurer, Zhicheng Wang
Techniques for Unit-Delay Compiled Simulation. DAC (1990)
Peter M. Maurer
Optimization of the Parallel Technique for Compiled Unit-Delay Simulation. ICCAD (1990)
Peter M. Maurer
The FHDL macro processor. ACM Southeast Regional Conference (1990)
Peter M. Maurer, Craig D. Morency
The FHDL ROM tools. ACM Southeast Regional Conference (1990)
Peter M. Maurer
Dynamic Functional Testing for VLSI Circuits. IEEE Des. Test Comput. 7 (6) (1990)
Peter M. Maurer
Generating Test Data with Enhanced Context-Free Grammars. IEEE Softw. 7 (4) (1990)
Zhicheng Wang, Peter M. Maurer
LECSIM: A Levelized Event Driven Compiled Logic Simulation. DAC (1990)
Zhicheng Wang, Peter M. Maurer
Scheduling High-Level Blocks for Functional Simulation. DAC (1989)
Peter M. Maurer
Design verification of the WE 32106 math accelerator unit. IEEE Des. Test 5 (3) (1988)
Peter M. Maurer, Alexander D. Schapira
A logic-to-logic comparator for VLSI layout verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (8) (1988)
Peter M. Maurer
Mapping the Data Flow Model of Computation into an Enhanced Von Neumann Processor. ICPP (1) (1988)
Peter M. Maurer, Arthur E. Oldehoeft
The Use of Combinators in Translating A Purely Functional Language to Low-Level Data-Flow Graphs. Comput. Lang. 8 (1) (1983)