Scheduling blocks of hierarchical compiled simulation of combinational circuits.
Peter M. MaurerPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1991)
Keyphrases
- scheduling problem
- asynchronous circuits
- high speed
- simulation models
- scheduling algorithm
- dynamic scheduling
- delay insensitive
- logic circuits
- image sequences
- mathematical model
- simulation model
- coarse to fine
- hierarchical model
- resource constraints
- data sets
- hierarchical clustering
- computational complexity
- information systems
- neural network